The present invention relates generally to semiconductor integrated circuits having a decreased electrode-to-electrode distance and a manufacturing method thereof. More particularly, but not exclusively, the invention relates to metal oxide semiconductor (MOS) transistors having the structure of narrowed gate electrode distance with the capability of eliminating the flow of leak current in a diffusion layer region between adjacent gate electrodes while increasing the operating speed of semiconductor integrated circuits.
Recent advances of micro-patterning/microfabrication technology in the manufacture of semiconductor elements have enabled attainment of higher integration of an increased number of devices on one chip, while simultaneously supporting the fundamental technical basis for development of high-performance devices.
One approach to meet the needs is to further increase the integration density of currently available stacked metal oxide semiconductor (MOS) transistors. The term xe2x80x9cstacked MOS transistorsxe2x80x9d as used herein may refer to those transistors with the device structure having a plurality of gate electrodes extending in parallel in the direction of the gate length. By way of example, since MOS transistors are such that the xe2x80x9cnaturexe2x80x9d of transistors (gate current) is determinable depending upon the ratio of gate width to gate length, it is possible to generate a required gate current which increases in magnitude as the gate width increases. Forming a plurality of gate electrodes of a constant gate width in a diffusion layer region of limited dimension may enable formation of plural MOS transistors. More specifically, forming two parallel gate electrodes having the same gate width on a substrate surface corresponding to such diffusion layer region makes it possible to configure circuitry including a combination of two MOS transistors.
FIG. 1 illustrates a plan view of one typical prior known NAND circuit comprised of a p-type MOS (pMOS) transistors and a n-type MOS (nMOS) transistor. As shown, the NAND circuit includes an n-type diffusion layer 223 and a p-type diffusion layer 224, above which gate electrodes 207 and 209 are formed. The diffusion layers 223, 224 have electrodes 227, 233 which are electrically connected together by metal lead patterns 235. Due to the inherent structure of the circuit, the distance xe2x80x9cAxe2x80x9d between the gate electrodes of nMOS transistors is less than the distance xe2x80x9cBxe2x80x9d between the gate electrodes of nMOS transistors. The gate distance xe2x80x9cAxe2x80x9d may typically be 300 nanometers (nm). The planar structure of one nMOS transistor and its operation will be described with reference to FIG. 2.
FIG. 2 is a plan view of one of the nMOS transistors constituting the NAND circuit with two gate electrodes formed insulatively overlying its diffusion layer. For example, the n-type diffusion layer 223 is formed in a semiconductor substrate, while parallel elongated gate electrodes 207, 209 are formed over the diffusion layer 223, wherein the gate electrode 207 is spaced apart from gate electrode 209 by a predefined distance that measures approximately 300 nm.
This prior art nMOS (part of the NAND circuit) transistor only generates a drain current when a voltage is applied to the electrodes 229, 231. In this case, a diffusion layer 223a may function as the source region, diffusion layer 223b serves as the drain region, and gate electrode 207 and 209 acts as the gate electrode, thus constituting a transistor which permits flow of a drain current from the source region 223a toward drain region 223b. Having two gate electrode (each gate width is thin) on one diffusion layer reduces the resistivity of the gate electrode. That increases the operation speed of the nMOS transistor.
FIGS. 3 through 6 which illustrate, in cross-section as taken on line A-Axe2x80x2 of FIG. 2, some of the major steps in the manufacture of the FIG. 2 MOS transistor in a time sequential order.
First, as shown in FIG. 3, a semiconductor substrate 201 made typically of silicon is prepared, which is then doped by well-known ion implantation techniques with a p-type impurity to a concentration of 4xc3x971016 atoms per cubic centimeter (4E16 cmxe2x88x923), forming a p-type well region 202 in the silicon substrate 201. An element separation region 203 is formed by selective oxidation techniques; then, a gate oxide film 205, of typically 6 nm thick, is formed by thermal oxidation on the p-well region 202 and element separation region 203. Next, a non-doped polycrystalline silicon (poly-silicon) layer having a thickness of approximately 200 nm is formed by chemical vapor deposition (CVD) techniques. The resulting polysilicon layer is then etched forming electrodes 207, 209. At this time, these electrodes 207, 209 are spaced apart from each other by about 300 nm, or more or less. Thereafter, an oxide film 206 is formed by low-pressure CVD (LPCVD) techniques on the gate oxide film 205 and electrodes 207, 209 as well as element separation region 203, to a thickness of for example 20 nm. Then, the p-well region 202 is doped by ion implantation with a chosen impurity such as arsenide through oxide film 206 at a dose of 3xc3x971014 atoms per square centimeter (3E14 1/cm2) while applying thereto an acceleration voltage of 60 kilo-electronvolts (keV), and is then thermally annealed for activation of the dopant at 950xc2x0 C. for 30 seconds to thereby form a xe2x80x9cshallowxe2x80x9d diffusion layer 211 (depth of 80 nm from the substrate surface) having xe2x80x9cthe extension structurexe2x80x9d of a sheet resistance of about 250 ohms per unit area (xcexa9/xe2x96xa1) as depicted in FIG. 3.
Next, as shown in FIG. 4, a silicon nitride film 217 is deposited by LPCVD to a thickness of typically 100 nm, overlying the entire top surface of the semiconductor substrate. When this is done, a xe2x80x9cgapxe2x80x9d space defined between the neighboring electrodes 207 and 209 is not completely burred and defines a narrow recess portion or xe2x80x9cgrovexe2x80x9d therebetween due to the fact that the distance between these electrodes 207, 209 is 300 nm.
Thereafter, as shown in FIG. 5, the silicon nitride film 217 is subjected to anisotropic etching with the oxide film 206 being used as a stopper for removal of the entire upper 100-nm part of film 217; the etching is terminated when the stopper film 206 is exposed at its top surface. At this time any silicon nitride deposited on the side walls of electrodes 207 and 209 still resides thereon, forming respective sidewall films 219 that are approximately 100 nm in maximal thickness. Next, with the sidewall films 219 used as a mask, the p-well region 202 is doped by ion implantation with a chosen impurity such as arsenide at an acceleration voltage of 65 keV to a dose of 5E15 (l/cm2), and is then annealed at 1050xc2x0 C. for about 10 seconds, thus forming a xe2x80x9cdeepxe2x80x9d diffusion layer 223 (its depth from the substrate surface is typically 150 nm, and its sheet resistance may be 60 (xcexa9/xe2x96xa1) as shown in FIG. 5.
Here, for a decrease in surface resistivity of the electrodes 207, 209 and diffusion layer 223 to speed up the operation of MOS transistors, one or more low-resistance silicides are formed near the electrodes by use of the salicide process, which will be explained as follows. First, the oxide film 206 is removed away using hydrofluoric acid solution with the sidewall films 219 used as a mask, exposing electrodes 207, 209 and diffusion 223. Then, titanium is entirely deposited by sputtering techniques on the exposed surface to a thickness of 30 nm or therearound, for formation of relatively high resistive silicides by a first-step annealing process at 750xc2x0 C. for 30 seconds. During this process the titanium exhibits silicide reaction only with silicon residing in such exposed region while allowing titanium in the other part thereof to be kept unreacted. Such unreacted titanium is then selectively removed using a 1:1 mixed solution of sulfuric acid and peroxide water, forcing specific part of silicon nitride on the electrodes 207, 209 and diffusion layer 223. Next, the relatively high resistive silicides are changed in composition or xe2x80x9ctransformedxe2x80x9d into low resistive silicides 225, by execution of a second-step annealing process at 850xc2x0 C. for 30 seconds. The resulting structure is depicted in FIG. 6.
Further, several additive components including well-known interlayer dielectric films and upper-layer lead patterns are formed overlying the electrodes 207, 209 to thereby complete an intended semiconductor integrated circuit (IC) comprised of MOS transistors.
As semiconductor ICs increase in integration density and in operating speed, it becomes inevitable to develop semiconductor ICs offering some structural features of a decreased distance between adjacent gate electrodes and less diffusion-layer capacitance. Also, as the demands for achievement of further increased circuit operation speed are becoming more strict in the recent years, the salicide technology for fabrication of low resistive silicides near electrodes is becoming increasingly important in a wide variety of semiconductor applications. The prior art semiconductor IC structure as discussed previously in conjunction with FIGS. 3-6 is the MOS IC device which applies such salicide process to its stacked MOS transistors satisfying the foregoing technical requirements for formation of low resistive silicides near the electrodes thereof.
It should be noted here that the salicide process is such that titanium is deposited by sputtering techniques for reaction with silicon by annealing, which in turn leads to the risk of occurrence of abnormal silicide growth due to some causes including, but not limited to, a reduction in silicide""s homology and a decrease in cohesive resistivity. See FIG. 7, which illustrates, in schematic cross-section, one exemplary semiconductor IC device that has experienced such silicide""s abnormal growth.
The distance between one gate electrode 207 and its neighboring gate electrode 209 measures 300 nm, more or less. The sidewall films 219 may approximately be 100 nm in maximal film thickness. Hence, the resulting xe2x80x9cgapxe2x80x9d space as defined between gate electrodes 207, 209 is about 100 nm. Where a silicide is formed by the salicide process in region of as narrow as 100 nm wide, the resultant silicide being formed on the surface of diffusion layer 223 can grow abnormally, which would result in unintentional downward break-through or xe2x80x9cextrusionxe2x80x9d of diffusion layer 223 to enter or xe2x80x9cinvadexe2x80x9d its underlying well region 202. In the worst case where silicide film 225 abnormally grows to enter the inside of well region 202 through diffusion 223, then junction leakage can take place between diffusion 223 and well region 202, which in turn behaves badly to cause operation failure or malfunction of MOS ICs fabricated.
A technique for avoiding such abnormal silicide growth is to increase the distance between the gate electrodes 207, 209 up to 600 nm or more; unfortunately, this does not come without accompanying a serious penalty: an increase in inherent gate-to-gate distance, which results in an increase in on-chip IC element occupation area per se. Another problem faced with the prior art is that simply increasing the distance between gate electrodes 207, 209 would result in an unwanted increase in inherent diffusion capacitance, which disadvantageously serves to lower the operability of semiconductor ICs.
It is therefore an object of the present invention to provide an improved structure and manufacturing method of a semiconductor integrated circuit device capable of exhibiting superior junction characteristics while at the same time decreasing the element area and increasing the operation speed even where the salicide technology is applied to an extremely narrowed part of diffusion layer laid between adjacent gate electrodes.
To attain the foregoing object, the present invention disclosed and claimed herein provides a specific semiconductor integrated circuit (IC) device which includes a couple of first and second, electrode layers formed in a semiconductor substrate, sidewall layers formed on the side walls of these first and second gate electrodes, and one or several high-melting point metal silicide layers as formed overlying the first and second gate electrodes, featured in that the first and second sidewall layers are connected together. Another feature of the IC device lies in that the high-melting point silicide layers were formed with the sidewall layers used as a mask pattern therefor.
The structural features of the instant invention make it possible to successfully eliminate, or at least greatly suppress, occurrence of any abnormal growth of silicides during formation thereof because of the fact that certain part or region of the semiconductor substrate is covered by the first and second sidewalls.
In accordance with a further aspect of the invention, a semiconductor IC device includes an impurity-doped layer formed in a semiconductor substrate, first and second electrode layers formed on the semiconductor substrate, a high-melting point metal layer formed in the impurity layer overlying the first and second electrode layers, and sidewall layers formed on the side walls of the first and second electrode layers, featured in that the first electrode layer is spaced apart from the second electrode layer by a specifically selected distance which may be less than or substantially equal to 200 nm. Alternatively, the distance between the first and second electrode layers is substantially less than the width of each of the first and second electrode layers.
With such second structural feature of the invention also, the risk of abnormal silicide growth beneath the region defined between the first and second gate electrodes may be avoidable because of the capability of forcing the first sidewall layer to be connected or coupled to the second sidewall layer due to a substantive decrease in distance between the first and second gate electrodes down to 200 nm or less. Additionally, the operation speed of the IC device may also be enhanced due to a decrease in diffusion capacitance as originated from the fact that the distance between the first and second gate electrodes remains less than before.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.